The continuous effort to improve semiconductor device performance brings with it a continuous effort of scaling down device feature sizes thereby improving the device performance speed and its functional capability. With the reduction in device feature sizes, the performance of the device becomes increasingly more dependent on the interconnections that are required between functional devices. In order to improve the interconnect aspect of semiconductor design and to reduce the relative impact of the device interconnects, integrated circuits are typically fabricated using multiple level interconnect schemes. The multiple layers of interconnect metalization contained within these multi-chip modules are typically separated by alternating layers of an isolating dielectric, the layers of dielectric serve as electrical isolation between the metal features. The metal that is used to construct the interconnect metal features is selected based on such performance characteristics as low resistivity, resistance to electromigration, adhesion to the underlying substrate material, stability (both electrical and mechanical), and ease of processing. For these reasons, copper is often selected due to its low resistivity, high electromigration resistance, and stress voiding resistance. Diffusion barrier layer is often deposited to line the trenches and vias (holes). The diffusion barrier layer sometimes also acts as an adhesion-promoting layer. For contact plugs, tungsten (W) is often used to fill the plugs, not copper, to prevent copper from diffusing to the gate. An adhesion layer is also used to line the contact plugs. With the reduction in device feature sizes, gap-fill of contact, via, and trench structures becomes increasingly challenging.
In addition to metal interconnect, the fabrication of gate electrodes for complementary metal-oxide-semiconductor (CMOS) transistors using high dielectric constant (high-k) dielectric material and metal to replace silicon dioxide and polysilicon also has challenging metal gap-fill issues. A replacement metal gate process is often used to form the gate electrode. A typical replacement metal gate process begins by forming a high-k dielectric material and a sacrificial gate between a pair of spacers on a semiconductor substrate. After further processing steps, the sacrificial gate is removed and the resulting trench is filled with one or more metal layers. Filling the one or more metal layers in the resulting trench has also become increasingly difficult due to shrinking device features.
Gap-filling of trench, via, contact, and replacement gate structures with metal films without voids to have good electrical and reliability performance is critical for advanced processing technologies. Therefore, there is a need for improved metal gap-fill processes for advanced semiconductor manufacturing technologies.